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PIC18F6585/8585/6680/8680

DS30491C-page 248

2004 Microchip Technology Inc.

18.4.2

USART SYNCHRONOUS SLAVE

RECEPTION

The operation of the Synchronous Master and Slave

modes is identical, except in the case of Sleep or any

Idle mode and bit SREN, which is a “don’t care” in

Slave mode.

If receive is enabled by setting the CREN bit prior to

entering Sleep or any Idle mode, then a word may be

received while in this low-power mode. Once the word

is received, the RSR register will transfer the data to the

RCREG register; if the RCIE enable bit is set, the inter-

rupt generated will wake the chip from low-power

mode. If the global interrupt is enabled, the program will

branch to the interrupt vector.

To set up a synchronous slave reception:

Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

If interrupts are desired, set enable bit RCIE.

If 9-bit reception is desired, set bit RX9.

To enable reception, set enable bit CREN.

Flag bit RCIF will be set when reception is

complete. An interrupt will be generated if

enable bit RCIE was set.

Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

Read the 8-bit received data by reading the

RCREG register.

If any error occurred, clear the error by clearing

bit CREN.

If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000

PIR1

PSPIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

PIE1

PSPIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

IPR1

PSPIP

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

1111 1111

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

RCREG

USART Receive Register

0000 0000

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

0000 0010

BAUDCON

—

RCIDL

—

SCKP

BRG16

—

WUE

ABDEN

-1-0 0-00

SPBRGH

Baud Rate Generator Register, High Byte

0000 0000

SPBRG

Baud Rate Generator Register, Low Byte

0000 0000

Legend:

= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

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